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ISP1582 hi-speed universal serial bus peripheral controller rev. 03 25 august 2004 preliminary data 1. general description the ISP1582 is a cost-optimized and feature-optimized hi-speed universal serial bus (usb) peripheral controller. it fully complies with universal serial bus speci?cation rev. 2.0 , supporting data transfer at high-speed (480 mbit/s) and full-speed (12 mbit/s). the ISP1582 provides high-speed usb communication capacity to systems based on microcontrollers or microprocessors. it communicates with a microcontroller or microprocessor of a system through a high-speed general-purpose parallel interface. the ISP1582 supports automatic detection of hi-speed usb system operation. original usb fall-back mode allows the device to remain operational under full-speed conditions. it is designed as a generic usb peripheral controller so that it can ?t into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. the internal generic direct memory access (dma) block allows easy integration into data streaming applications. the modular approach to implementing a usb peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. the ability to reuse existing architecture and ?rmware investments shortens the development time, eliminates risk and reduces cost. the result is fast and ef?cient development of the most cost-effective usb peripheral solution. the ISP1582 is ideally suited for many types of peripherals, such as: printers, scanners, digital still cameras, usb-to-ethernet links, cable and dsl modems. the low power consumption during suspend mode allows easy design of equipment that is compliant to the acpi?, onnow? and usb power management requirements. the ISP1582 also incorporates features such as softconnect?, a reduced frequency crystal oscillator, and integrated termination resistors. these features allow signi?cant cost savings in system design and easy implementation of advanced usb functionality into pc peripherals.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 2 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. features n complies fully with: u universal serial bus speci?cation rev. 2.0 u most device class speci?cations u acpi?, onnow? and usb power management requirements. n supports data transfer at high-speed (480 mbit/s) and full-speed (12 mbit/s) n high performance usb peripheral controller with integrated serial interface engine (sie), parallel interface engine (pie), fifo memory and data transceiver n automatic hi-speed usb mode detection and original usb fall-back mode n supports sharing mode n supports v bus sensing n high-speed dma interface n fully autonomous and multicon?guration dma operation n 7 in endpoints, 7 out endpoints and a ?xed control in/out endpoint n integrated physical 8 kbytes of multicon?guration fifo memory n endpoints with double buffering to increase throughput and ease real-time data transfer n bus-independent interface with most microcontrollers and microprocessors n 12 mhz crystal oscillator with integrated pll for low emi n software-controlled connection to the usb bus (softconnect?) n low-power consumption in operation and power-down modes; suitable for use in bus-powered usb devices n supports session request protocol (srp) that complies with on-the-go supplement to the usb speci?cation rev. 1.0a n internal power-on and low-voltage reset circuits; also supports software reset n operation over the extended usb bus voltage range (dp, dm and v bus ) n 5 v tolerant i/o pads at 3.3 v n operating temperature range from - 40 c to +85 c n available in hvqfn56 halogen-free and lead-free package. 3. applications n personal digital assistant n digital video camera n digital still camera n 3g mobile phone n mp3 player n communication device, for example: router and modem n printer n scanner.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 3 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. abbreviations dma direct memory access emi electromagnetic interference fs full-speed gdma generic dma hs high-speed mmu memory management unit nrzi non-return-to-zero inverted otg on-the-go pda personal digital assistant pid packet identi?er pie parallel interface engine pio parallel input/output pll phase-locked loop se0 single-ended zero sie serial interface engine srp session request protocol usb universal serial bus. 5. ordering information table 1: ordering information type number package name description version ISP1582bs hvqfn56 plastic thermal enhanced very thin quad ?at package; no leads; 56 terminals; body 8 8 0.85 mm sot684-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors ISP1582 hi-speed usb peripheral controller 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data rev. 03 25 august 2004 4 of 66 6. block diagram fig 1. block diagram. 1.5 k w 12.0 k w v cc 004aaa199 ISP1582 memory management unit integrated ram (8 kbytes) system controller voltage regulators power-on reset hi-speed usb transceiver internal reset softconnect analog supply digital supply i/o pad supply micro- controller handler micro- controller interface otg srp module dma registers dma handler dma interface philips sie/pie int data [ 15:0 ] a [ 7:0 ] 8 dack 3.3 v v cc(1v8) suspend wakeup agnd dgnd 3.3 v rd_n eot v cc(i/o) 16 1, 5 2 7 8 dreq dior diow 9101112 13, 26, 29, 41 14 cs_n wr_n 15 16 17 18 to 20, 22 to 25, 27 21, 34, 48 28, 50 30 to 33, 35 to 40, 42 to 47 12 mhz xtal2 xtal1 to/from usb dm dp v bus 4 3495251 53, 54 55 56 6 rpu rref reset_n
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 5 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. pinning information 7.1 pinning fig 2. pin con?guration hvqfn56 (top view). fig 3. pin con?guration hvqfn56 (bottom view). data0 data1 data2 data10 v cc(i/o) data4 data5 data6 data7 data8 data9 dgnd data13 data14 cs_n rd_n wr_n a1 a2 a3 a4 a5 a6 dgnd a7 v cc(1v8) suspend data15 v cc(1v8) v bus xtal1 xtal2 data12 data11 v cc v cc(i/o) data3 wakeup v cc dgnd v cc(i/o) a0 004aaa536 ISP1582bs 13 14 12 11 10 9 6 8 45 51 53 49 47 46 48 50 52 54 55 56 26 21 24 25 43 44 28 27 23 22 20 19 17 15 18 16 4 7 5 3 29 31 34 33 30 32 35 36 38 40 37 39 2 1 42 41 int diow dior dgnd dreq dack reset_n eot agnd dm rref rpu agnd dp dgnd data9 data8 dgnd data6 data5 data4 v cc(i/o) data3 data2 data1 data0 dgnd a6 agnd dp dm rpu rref agnd eot reset_n dack dior dreq dgnd int suspend wakeup v cc xtal1 xtal2 v bus v cc(i/o) data15 data14 data13 data12 data11 cs_n a5 v cc(i/o) a3 diow a1 a2 a7 v cc(1v8) a0 a4 data7 rd_n wr_n data10 v cc(1v8) v cc 004aaa377 ISP1582bs 2 1 3 4 5 6 9 7 26 20 18 22 24 25 23 21 19 17 16 15 45 50 47 46 28 27 43 44 48 49 51 52 54 56 53 55 11 8 10 12 42 40 37 38 41 39 36 35 33 31 34 32 13 14 29 30 bottom view terminal 1 gnd (exposed die pad)
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 6 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.2 pin description table 2: pin description symbol [1] pin type [2] description agnd 1 - analog ground rpu 2 a connect to the external pull-up resistor for pin dp; must be connected to 3.3 v via a 1.5 k w resistor dp 3 a usb d+ line connection (analog) dm 4 a usb d - line connection (analog) agnd 5 - analog ground rref 6 a connect to the external bias resistor; must be connected to ground via a 12.0 k w 1 % resistor reset_n 7 i reset input (500 m s); a low level produces an asynchronous reset; connect to v cc for the power-on reset (internal por circuit) ttl; 5 v tolerant eot 8 i end-of-transfer input (programmable polarity); used in dma slave mode only; when not in use, connect this pin to v cc(i/o) through a 10 k w resistor input pad; ttl; 5 v tolerant dreq 9 o dma request (programmable polarity) output; when not in use, connect this pin to ground through a 10 k w resistor; see ta b l e 5 4 and ta b l e 5 5 ttl; 4 ns slew-rate control dack 10 i dma acknowledge input (programmable polarity); when not in use, connect this pin to v cc(i/o) through a 10 k w resistor; see ta bl e 5 4 and ta b l e 5 5 ttl; 5 v tolerant dior 11 i dma read strobe input (programmable polarity); when not in use, connect this pin to v cc(i/o) through a 10 k w resistor; see ta b l e 5 4 and ta b l e 5 5 ttl; 5 v tolerant diow 12 i dma write strobe input (programmable polarity); when not in use, connect this pin to v cc(i/o) through a 10 k w resistor; see ta b l e 5 4 and ta b l e 5 5 ttl; 5 v tolerant dgnd 13 - digital ground int 14 o interrupt output; programmable polarity (active high or low) and signaling (edge or level triggered) cmos output; 8 ma drive cs_n 15 i chip select input input pad; ttl; 5 v tolerant rd_n 16 i read strobe input input pad; ttl; 5 v tolerant wr_n 17 i write strobe input input pad; ttl; 5 v tolerant
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 7 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. a0 18 i bit 0 of the address bus input pad; ttl; 5 v tolerant a1 19 i bit 1 of the address bus input pad; ttl; 5 v tolerant a2 20 i bit 2 of the address bus input pad; ttl; 5 v tolerant v cc(i/o) [3] 21 - supply voltage; used to supply voltage to the i/o pads; see section 8.14 a3 22 i bit 3 of the address bus input pad; ttl; 5 v tolerant a4 23 i bit 4 of the address bus input pad; ttl; 5 v tolerant a5 24 i bit 5 of the address bus input pad; ttl; 5 v tolerant a6 25 i bit 6 of the address bus input pad; ttl; 5 v tolerant dgnd 26 - digital ground a7 27 i bit 7 of the address bus input pad; ttl; 5 v tolerant v cc(1v8) [3] 28 - regulator output voltage (1.8 v 0.15 v); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using a 0.1 m f capacitor; see section 8.14 dgnd 29 - digital ground data0 30 i/o bit 0 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data1 31 i/o bit 1 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data2 32 i/o bit 2 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data3 33 i/o bit 3 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant v cc(i/o) [3] 34 - supply voltage; used to supply voltage to the i/o pads; see section 8.14 data4 35 i/o bit 4 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data5 36 i/o bit 5 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data6 37 i/o bit 6 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data7 38 i/o bit 7 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 8 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. data8 39 i/o bit 8 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data9 40 i/o bit 9 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant dgnd 41 - digital ground data10 42 i/o bit 10 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data11 43 i/o bit 11 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data12 44 i/o bit 12 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data13 45 i/o bit 13 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data14 46 i/o bit 14 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant data15 47 i/o bit 15 of bidirectional data bus bidirectional pad; 4 ns slew-rate control; ttl; 5 v tolerant v cc(i/o) [3] 48 - supply voltage; used to supply voltage to the i/o pads; see section 8.14 v bus 49 a usb bus power pin sensing input; used to detect whether the host is connected or not; it is an output for v bus pulsing in otg mode; when v bus is not detected, pin rpu is internally disconnected from pin dp in approximately 4 ns; connect a 1 m f electrolytic capacitor and a 1 m w pull-down resistor to ground; see section 8.12 5 v tolerant v cc(1v8) [3] 50 - regulator output voltage (1.8 v 0.15 v); tapped out voltage from the internal regulator; this regulated voltage can drive external devices up to 1 ma; decouple this pin using 4.7 m f and 0.1 m f capacitors; see section 8.14 xtal2 51 o crystal oscillator output (12 mhz); connect a fundamental parallel-resonant crystal; leave this pin open-circuit when using an external clock source on pin xtal1; see ta b l e 8 3 xtal1 52 i crystal oscillator input (12 mhz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin xtal2 unconnected); see ta bl e 8 3 v cc [3] 53 - supply voltage (3.3 v 0.3 v); this pin supplies the internal voltage regulator and the analog circuit; see section 8.14 v cc [3] 54 - supply voltage (3.3 v 0.3 v); this pin supplies the internal voltage regulator and the analog circuit; see section 8.14 table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 9 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names ending with underscore n (for example, name_n) represent active low signals. [2] all outputs and i/o pins can source 4 ma. [3] add a decoupling capacitor (0.1 m f) to all the supply pins. for better emi results, add a 0.01 m f capacitor in parallel to the 0.1 m f. wakeup 55 i wake-up input; when this pin is at the high level, the chip is prevented from getting into the suspend state and the chip wakes up from the suspend state; when not in use, connect this pin to ground through a 10 k w resistor input pad; ttl; 5 v tolerant suspend 56 o suspend state indicator output; used as a power switch control output for powered-off application or as a resume signal to the cpu for powered-on application cmos output; 8 ma drive gnd exposed die pad - ground supply; down bonded to the exposed die pad (heatsink); to be connected to dgnd during pcb layout table 2: pin description continued symbol [1] pin type [2] description
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 10 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description the ISP1582 is a high-speed usb peripheral controller. it implements the hi-speed usb or the original usb physical layer and the packet protocol layer. it maintains up to 16 usb endpoints concurrently (control in and control out, 7 in and 7 out con?gurable) along with endpoint ep0 setup, which accesses the setup buffer. the usb chapter 9 protocol handling is executed by means of external ?rmware. for high-bandwidth data transfer, the integrated dma handler can be invoked to transfer data to or from external memory or devices. the dma interface can be con?gured by writing to the proper dma registers (see section 9.4 ). the ISP1582 supports hi-speed usb and original usb signaling. the usb signaling speed is automatically detected. the ISP1582 has 8 kbytes of internal fifo memory, which is shared among the enabled usb endpoints. there are 7 in endpoints, 7 out endpoints and 2 control endpoints that are a ?xed 64 bytes long. any of the 7 in and 7 out endpoints can be separately enabled or disabled. the endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually con?gured depending on the requirements of the application. optional double buffering increases the data throughput of these data endpoints. the ISP1582 requires 3.3 v power supply. it has 5 v tolerant i/o pads when operating at v cc(i/o) = 3.3 v and an internal 1.8 v regulator for powering the analog transceiver. the ISP1582 operates on a 12 mhz crystal oscillator. an integrated 40 pll clock multiplier generates the internal sampling clock of 480 mhz. 8.1 dma interface, dma handler and dma registers the dma block can be subdivided into two blocks: the dma handler and the dma interface. the ?rmware writes to the dma command register to start a dma transfer (see ta b l e 4 7 ). the command opcode determines whether a generic dma or pio transfer will start. the handler interfaces to the same fifo (internal ram) as used by the usb core. on receiving the dma command, the dma handler directs the data from the endpoint fifo to the external dma device or from the external dma device to the endpoint fifo. the dma interface con?gures the timing and the dma handshake. data can be transferred using either the dior and diow strobes or by the dack and dreq handshakes. the dma con?gurations are set up by writing to the dma con?guration register (see ta b l e 5 2 and ta b l e 5 3 ). for a generic dma interface, generic dma (gdma) slave mode can be used. remark: the dma endpoint buffer length must be a multiple of 4 bytes. for details on dma registers, see section 9.4 .
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 11 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.2 hi-speed usb transceiver the analog transceiver directly interfaces to the usb cable through integrated termination resistors. the high-speed transceiver requires an external resistor (12.0 k w 1 %) between pin rref and ground to ensure an accurate current mirror that generates the hi-speed usb current drive. a full-speed transceiver is integrated as well. this makes the ISP1582 compliant to hi-speed usb and original usb, supporting both the high-speed and full-speed physical layers. after automatic speed detection, the philips serial interface engine (sie) sets the transceiver to use either high-speed or full-speed signaling. 8.3 mmu and integrated ram the memory management unit (mmu) and the integrated ram provide the conversion between the usb speed (full-speed: 12 mbit/s, high-speed: 480 mbit/s) and the microcontroller handler or the dma handler. the data from the usb bus is stored in the integrated ram, which is cleared only when the microcontroller has read or written all data from or to the corresponding endpoint buffer or when the dma handler has read or written all data from or to the endpoint buffer. the out endpoint buffer can also be cleared forcibly by setting bit clbuf in the control function register. a total of 8 kbytes ram is available for buffering. 8.4 microcontroller interface and microcontroller handler the microcontroller handler allows the external microcontroller or microprocessor to access the register set in the philips sie as well as the dma handler. the initialization of the dma con?guration is done through the microcontroller handler. 8.5 otg srp module the otg supplement de?nes a session request protocol (srp), which allows a b-device to request the a-device to turn on v bus and start a session. this protocol allows the a-device, which may be battery-powered, to conserve power by turning off v bus when there is no bus activity while still providing a means for the b-device to initiate bus activity. any a-device, including a pc or laptop, can respond to srp. any b-device, including a standard usb peripheral, can initiate srp. the ISP1582 is a device that can initiate srp. 8.6 philips high-speed transceiver 8.6.1 philips parallel interface engine (pie) in the high-speed (hs) transceiver, the philips pie interface uses a 16-bit parallel bidirectional data interface. the functions of the hs module also include bit-stuf?ng or destuf?ng and non-return-to-zero inverted (nrzi) encoding or decoding logic. 8.6.2 peripheral circuit to maintain a constant current driver for hs transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an rref resistor form the reference current. this circuit requires an external precision resistor (12.0 k w 1%) connected to the analog ground.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 12 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6.3 hs detection the ISP1582 handles more than one electrical statefull-speed (fs) or high-speed (hs)under the usb speci?cation. when the usb cable is connected from the peripheral to the host controller, the ISP1582 defaults to the fs state until it sees a bus reset from the host controller. during the bus reset, the peripheral initiates an hs chirp to detect whether the host controller supports hi-speed usb or original usb. chirping must be done with the pull-up resistor connected and the internal termination resistors disabled. if the hs handshake shows that there is an hs host connected, then the ISP1582 switches to the hs state. in the hs state, the ISP1582 should observe the bus for periodic activity. if the bus remains inactive for 3 ms, the peripheral switches to the fs state to check for a single-ended zero (se0) condition on the usb bus. if an se0 condition is detected for the designated time (100 m s to 875 m s; refer to section 7.1.7.6 of the usb speci?cation rev. 2.0), the ISP1582 switches to the hs chirp state to perform an hs detection handshake. otherwise, the ISP1582 remains in the fs state adhering to the bus-suspend speci?cation. 8.7 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit (de)stuf?ng, crc checking or generation, packet identi?er (pid) veri?cation or generation, address recognition, handshake evaluation or generation. 8.8 softconnect the connection to the usb is established by pulling pin dp (for full-speed devices) high through a 1.5 k w pull-up resistor. in the ISP1582, an external 1.5 k w pull-up resistor must be connected between pin rpu and 3.3 v. pin rpu connects the pull-up resistor to pin dp, when bit softct in the mode register is set (see ta b l e 2 0 and ta b l e 2 1 ). after a hardware reset, the pull-up resistor is disconnected by default (bit softct = 0). the usb bus reset does not change the value of bit softct. when the v bus is not present, the softct bit must be set to logic 0 to comply with the back-drive voltage. 8.9 system controller the system controller implements the usb power-down capabilities of the ISP1582. registers are protected against data corruption during wake-up following a resume (from the suspend state) by locking the write access until an unlock code has been written in the unlock device register (see ta b l e 7 3 and ta b l e 7 4 ). 8.10 output pins status ta b l e 3 illustrates the behavior of output pins when v cc(i/o) is supplied with v cc in various operating conditions.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 13 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] x: dont care. [2] dead: the usb cable is plugged-out and v cc(i/o) is not available. [3] plug-out: the usb cable is not present but v cc(i/o) is available. [4] plug-in: the usb cable is being plugged-in and v cc(i/o) is available. 8.11 interrupt 8.11.1 interrupt output pin the interrupt con?guration register of the ISP1582 controls the behavior of the int output pin. the polarity and signaling mode of pin int can be programmed by setting bits intpol and intlvl of the interrupt con?guration register (r/w: 10h); see ta b l e 2 4 . bit glintena of the mode register (r/w: och) is used to enable pin int. default settings after reset are active low and level mode. when pulse mode is selected, a pulse of 60 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. figure 4 shows the relationship between the interrupt events and pin int. each of the indicated usb and dma events is logged in a status bit of the interrupt register and the dma interrupt reason register, respectively. corresponding bits in the interrupt enable register and the dma interrupt enable register determine whether or not an event will generate an interrupt. interrupts can be masked globally by means of bit glintena of the mode register; see ta b l e 2 1 . field cdbgmod[1:0] of the interrupt con?guration register controls the generation of the int signals for the control pipe. field ddbgmodin[1:0] of the interrupt con?guration register controls the generation of the int signals for the in pipe. field ddbgmodout[1:0] of the interrupt con?guration register controls the generation of the int signals for the out pipe; see ta b l e 2 5 . table 3: ISP1582 pin status [1] v cc v cc(i/o) state pin reset_n int_n suspend dreq data[15:0] 0v v cc dead [2] xxxxx 0v v cc plug-out [3] x low high high-z input 0v -> 3.3 v v cc plug-in [4] x low high high-z high-z 3.3 v v cc reset low high low high-z high-z 3.3 v v cc normal high high low high-z high-z
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors ISP1582 hi-speed usb peripheral controller 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data rev. 03 25 august 2004 14 of 66 fig 4. interrupt logic. or interrupt register dma interrupt reason register dma interrupt enable register interrupt enable register dma_xfer_ok ext_eot int_eot ie_dma_xfer_ok ie_ext_eot ie_int_eot or iebreset iesof iedma iep7rx iep7tx breset sof dma ep7rx ep7tx ...... .... ...... .... ...... .... 004aaa275 latch glintena intpol le interrupt configuration register mode register int pulse/level generator
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 15 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.11.2 interrupt control bit glintena in the mode register is a global enable/disable bit. the behavior of this bit is given in figure 5 . event a: when an interrupt event occurs (for example, sof interrupt) with bit glintena set to logic 0, an interrupt will not be generated at pin int. it will, however, be registered in the corresponding interrupt register bit. event b: when bit glintena is set to logic 1, pin int is asserted because bit sof in the interrupt register is already set. event c: if the ?rmware sets bit glintena to logic 0, pin int will still be asserted. the bold dashed line shows the desired behavior of pin int. deassertion of pin int can be achieved either by clearing all the interrupt register or the dma interrupt reason register, depending on the event. remark: when clearing an interrupt event, perform write to all the bytes of the register. for more information on interrupt control, see section 9.2.2 , section 9.2.5 and section 9.5.1 . 8.12 v bus sensing pin v bus is one of the ways to wake up the clock when the ISP1582 is suspended with bit clkaon set to logic 0 (clock off option). to detect whether the host is connected or not, that is v bus sensing, a 1 m w resistor and a 1 m f electrolytic capacitor must be added to damp the overshoot upon plug-in. pin int: high = deassert; low = assert (individual interrupts are enabled). fig 5. behavior of bit glintena. int pin 004aaa394 glintena = 0 sof asserted glintena = 1 sof asserted glintena = 0 (during this time, an interrupt event occurs. for example, sof asserted.) a b c fig 6. resistor and electrolytic capacitor needed for v bus sensing. 1 m w ISP1582 004aaa440 + 1 f 49 usb connector
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 16 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.13 power-on reset the ISP1582 requires a minimum pulse width of 500 m s. pin reset_n can be either connected to v cc (using the internal por circuit) or externally controlled (by the microcontroller, asic, and so on). when v cc is directly connected to pin reset_n, the internal pulse width t porp will be typically 200 ns. the power-on reset function can be explained by viewing the dips at t2-t3 and t4-t5 on the v cc(por) curve ( figure 9 ). t0 the internal por starts with a high level. t1 the detector will see the passing of the trip level and a delay element will add another t porp before it drops to low. t2-t3 the internal por pulse will be generated whenever v cc(por) drops below v trip for more than 11 m s. t4-t5 the dip is too short (< 11 m s) and the internal por pulse will not react and will remain low. figure 10 shows the availability of the clock with respect to the external por. fig 7. oscilloscope reading: no resistor and capacitor in the network. fig 8. oscilloscope reading: with resistor and capacitor in the network. 004aaa441 004aaa442 (1) porp = power-on reset pulse. fig 9. por timing. 004aaa389 v bat(por) t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 17 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14 power supply the ISP1582 can be powered by 3.3 v 0.3 v, and 3.3 v at the interface. for connection details, see figure 11 . if the ISP1582 is powered by v cc = 3.3 v, an integrated 3.3 v-to-1.8 v voltage regulator provides a 1.8 v supply voltage for the internal logic. in sharing mode (that is, when v cc is not present and v cc(i/o) is present), all the i/o pins are in three-state, the interrupt pin is connected to ground, and the suspend pin is connected to v cc(i/o) . see ta b l e 3 . stable external clock is to be available at a. fig 10. clock with respect to the external por. por external clock a 004aaa365 (1) it is mandatory to use a 4.7 m f electrolytic capacitor on v cc(1v8) . fig 11. ISP1582 with 3.3 v supply. 004aaa203 53, 54 v cc(i/o) ISP1582 3.3 v 0. 3 v v cc(i/o) v cc 48 34 v cc(i/o) v cc(1v8) 21 50 4.7 f (1) 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f 0.01 f 0.1 f v cc(1v8) 28 0.1 f + v cc
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 18 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. ta b l e 4 shows power modes in which the ISP1582 can be operated. [1] power supply to the ic (v cc ) is 3.3 v. therefore, if the application is bus-powered, a 3.3 v regulator needs to be used. [2] v cc(i/o) =v cc . if the application is bus-powered, a voltage regulator needs to be used. 8.14.1 power-sharing mode as can be seen in figure 12 , in power-sharing mode, v cc is supplied by the output of the 5 v-to-3.3 v voltage regulator. the input to the regulator is from v bus . v cc(i/o) is supplied through the power source of the system. when the usb cable is plugged in, the ISP1582 goes through the power-on reset cycle. in this mode, otg is disabled. the processor will experience continuous interrupt because the default status of the interrupt pin when operating in sharing mode with the v bus not present is low. to overcome this, implement external v bus sensing circuitry. the output from the voltage regulator can be connected to pin gpio of the processor to qualify the interrupt from the ISP1582. remark: when the core power is removed, the ISP1582 must be reset using the reset_n pin. the reset pulse width must be 2 ms. table 4: power modes v cc v cc(i/o) power mode v bus [1] v bus [2] bus-powered self-powered self-powered self-powered v bus [1] self-powered power-sharing (hybrid) fig 12. power-sharing mode. 004aaa457 ISP1582 + - 5 v-to-3.3 v usb voltage regulator to gpio of processor for sensing v bus 1 m w v cc v cc(i/o) v bus rpu v bus 1 f + - 1.5 k w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 19 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 13. interrupt pin status during power off in power-sharing mode. table 5: operation truth table for softconnect ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled core power is lost 0 v 3.3 v 0 v 0 v not applicable table 6: operation truth table for clock off during suspend ISP1582 operation power supply clock off during suspend v cc v cc(i/o) rpu (3.3 v) v bus clock will wake up: after resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled core power is lost 0 v 3.3 v 0 v 0 v not applicable table 7: operation truth table for back voltage compliance ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled back voltage is not an issue because core power is lost 0 v 3.3 v 0 v 0 v not applicable table 8: operation truth table for otg ISP1582 operation power supply otg register v cc v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable otg is not possible because v bus is not present and so core power is lost 0 v 3.3 v 0 v 0 v not applicable 004aaa469 v cc(i/o) v cc int power off power off
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 20 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.2 self-powered mode in self-powered mode, v cc and v cc(i/o) are supplied by the system. bit softct in the mode register must be always logic 1. see figure 14 . [1] when the usb cable is removed, softconnect is disabled. fig 14. self-powered mode. table 9: operation truth table for softconnect ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled no pull-up on dp 3.3 v 3.3 v 3.3 v 0 v [1] disabled table 10: operation truth table for clock off during suspend ISP1582 operation power supply clock off during suspend v cc v cc(i/o) rpu (3.3 v) v bus clock will wake up: after resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled clock will wake up: after detecting the presence of v bus 3.3 v 3.3 v 3.3 v 0 v => 5 v enabled table 11: operation truth table for back voltage compliance ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled back voltage is not an issue because pull-up on dp will not be present when v bus is not present 3.3 v 3.3 v 3.3 v 0 v disabled 004aaa460 ISP1582 + - usb 1 m w v cc v cc(i/o) v bus rpu v bus 1.5 k w 1 f + -
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 21 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.3 bus-powered mode in bus-powered mode (see figure 15 ), v cc and v cc(i/o) are supplied by the output of the 5 v-to-3.3 v voltage regulator. the input to the regulator is from v bus . on plugging in of the usb cable, the ISP1582 goes through the power-on reset cycle. in this mode, otg is disabled. table 12: operation truth table for otg ISP1582 operation power supply otg register v cc v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable srp is possible 3.3 v 3.3 v 3.3 v 0 v operational fig 15. bus-powered mode. table 13: operation truth table for softconnect ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus normal bus operation 3.3 v 3.3 v 3.3 v 5 v enabled power loss 0 v 0 v 0 v 0 v not applicable table 14: operation truth table for clock off during suspend ISP1582 operation power supply clock off during suspend v cc v cc(i/o) rpu (3.3 v) v bus clock will wake up: after resume and after a bus reset 3.3 v 3.3 v 3.3 v 5 v enabled power loss 0 v 0 v 0 v 0 v not applicable 004aaa462 ISP1582 5 v-to-3.3 v usb voltage regulator 1 m w v cc v cc(i/o) v bus v bus rpu 1 f + - 1.5 k w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 22 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 15: operation truth table for back voltage compliance ISP1582 operation power supply bit softct in mode register v cc v cc(i/o) rpu (3.3 v) v bus back voltage is not measured in this mode 3.3 v 3.3 v 3.3 v 5 v enabled power loss 0 v 0 v 0 v 0 v not applicable table 16: operation truth table for otg ISP1582 operation power supply otg register v cc v cc(i/o) rpu (3.3 v) v bus srp is not applicable 3.3 v 3.3 v 3.3 v 5 v not applicable power loss 0 v 0 v 0 v 0 v not applicable
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 23 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. register description table 17: register overview name destination address description size (bytes) reference initialization registers address device 00h usb device address and enabling 1 section 9.2.1 on page 24 mode device 0ch power-down options, global interrupt enable, softconnect 1 section 9.2.2 on page 25 interrupt con?guration device 10h interrupt sources, trigger mode, output polarity 1 section 9.2.3 on page 27 otg device 12h otg implementation 1 section 9.2.4 on page 28 interrupt enable device 14h interrupt source enabling 4 section 9.2.5 on page 30 data ?ow registers endpoint index endpoints 2ch endpoint selection, data ?ow direction 1 section 9.3.1 on page 31 control function endpoint 28h endpoint buffer management 1 section 9.3.2 on page 33 data port endpoint 20h data access to endpoint fifo 2 section 9.3.3 on page 33 buffer length endpoint 1ch packet size counter 2 section 9.3.4 on page 34 buffer status endpoint 1eh buffer status for each endpoint 1 section 9.3.5 on page 35 endpoint maxpacketsize endpoint 04h maximum packet size 2 section 9.3.6 on page 36 endpoint type endpoint 08h selects endpoint type: control, isochronous, bulk or interrupt 2 section 9.3.7 on page 37 dma registers dma command dma controller 30h controls all dma transfers 1 section 9.4.1 on page 39 dma transfer counter dma controller 34h sets byte count for dma transfer 4 section 9.4.2 on page 40 dma con?guration dma controller 38h sets gdma con?guration (counter enable, burst length, data strobing, bus width) 1 section 9.4.3 on page 41 dma hardware dma controller 3ch endian type, master or slave selection, signal polarity for dack, dreq, diow, dior 1 section 9.4.4 on page 42 dma interrupt reason dma controller 50h shows reason (source) for dma interrupt 2 section 9.4.5 on page 43 dma interrupt enable dma controller 54h enables dma interrupt sources 2 section 9.4.6 on page 45 dma endpoint dma controller 58h selects endpoint fifo, data ?ow direction 1 section 9.4.7 on page 45
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 24 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.1 register access register access depends on the bus width used. the ISP1582 uses a 16-bit bus access. for single-byte registers, the upper byte (msbyte) must be ignored. endpoint speci?c registers are indexed via the endpoint index register. the target endpoint must be selected before accessing the following registers: ? buffer length ? buffer status ? control function ? data port ? endpoint maxpacketsize ? endpoint type. remark: all reserved bits are not implemented. the bus and bus reset values are not de?ned. therefore, writing to these reserved bits will have no effect. 9.2 initialization registers 9.2.1 address register (address: 00h) this register sets the usb assigned address and enables the usb device. ta b l e 1 8 shows the address register bit allocation. bits devaddr will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. bit deven will be cleared whenever a power-on reset or a soft reset occurs, and will be set after a bus reset. dma burst counter dma controller 64h dma burst counter 2 section 9.4.8 on page 46 general registers interrupt device 18h shows interrupt sources 4 section 9.5.1 on page 46 chip id device 70h product id code and hardware version 3 section 9.5.2 on page 48 frame number device 74h last successfully received start-of-frame: lower byte (byte 0) is accessed ?rst 2 section 9.5.3 on page 49 scratch device 78h allows save or restore of ?rmware status during suspend 2 section 9.5.4 on page 49 unlock device device 7ch reenables register access after suspend 2 section 9.5.5 on page 50 test mode phy 84h direct setting of dp and dm states, internal transceiver test (phy) 1 section 9.5.6 on page 51 table 17: register overview continued name destination address description size (bytes) reference
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 25 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. in response to the standard usb request set_address, the ?rmware must write the (enabled) device address to the address register, followed by sending an empty packet to the host. the new device address is activated when the device receives acknowledgment from the host. 9.2.2 mode register (address: 0ch) this register consists of 2 bytes (bit allocation: see ta b l e 2 0 ). the mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and softconnect operation. table 18: address register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devaddr[6:0] reset 00000000 bus reset 10000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 19: address register: bit description bit symbol description 7 deven logic 1 enables the device. 6 to 0 devaddr[6:0] this ?eld speci?es the usb device address. table 20: mode register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved dma clkon vbusstat reset ------0- bus reset ------0- access rrrrrrr/wr bit 7 6 5 4 3 2 1 0 symbol clkaon sndrsu gosusp sfreset glintena wkupcs pwron softct reset 00000000 bus reset 0000 unchanged 0 0 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 21: mode register: bit description bit symbol description 15 to 10 - reserved 9 dmaclkon 1 supply clock to the dma circuit. 0 power save mode; the dma circuit will stop completely to save power. 8 vbusstat this bit re?ects the v bus pin status.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 26 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. when softconnect and v bus are not present (except in otg), the usb bus activities are not quali?ed. therefore, the chip will follow the suspend command to enter suspend mode (the clock is controlled by bit clkaon). when v bus is off, the 1.5 k w pull-up resister is disconnected from pin dp in approximately 4 ns via bit softct in the mode register and a suspend interrupt is set with some latency (debounce and disqualify usb traf?c). when bit softct is set to logic 0, no interrupt is generated. the ?rmware can issue a suspend command, followed by the resetting of bit softct to suspend the chip. if otg is logic 1, the pull-up resistor on pin dp depends on d+ line (v bus sensing status). bit dp operates as normal, so the ?rmware must mask suspend and wake-up interrupt events. when srp is completed, the device should clear otg. 7 clkaon clock always on: logic 1 indicates that the internal clocks are always running when in the suspend state. logic 0 switches off the internal oscillator and pll when the device goes into suspend mode. the device will consume less power if this bit is set to logic 0. the clock is stopped after a delay of approximately 2 ms, following which bit gosusp is set. 6 sndrsu send resume: writing logic 1, followed by logic 0 will generate an upstream resume signal of 10 ms duration, after a 5 ms delay. 5 gosusp go suspend: writing logic 1, followed by logic 0 will activate suspend mode. 4 sfreset soft reset: writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1582. a soft reset is similar to a hardware-initiated reset (via pin reset_n). 3 glintena global interrupt enable: logic 1 enables all interrupts. individual interrupts can be masked by clearing the corresponding bits in the interrupt enable register. when this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. if global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will be immediately generated on the interrupt pin. (if the interrupt is set to pulse mode, the interrupt events that were generated before the global interrupt is enabled may be dropped). 2 wkupcs wake up on chip select: logic 1 enables wake-up from suspend mode through a valid register read on the ISP1582. (a read will invoke the chip clock to restart. if you write to the register before the clock gets stable, it may cause malfunctioning). 1 pwron pin suspend output control. 0 pin suspend is high when the ISP1582 is in the suspend state. otherwise, pin suspend is low. 1 when the device is woken up from the suspend state, there will be a 1 ms active high pulse on pin suspend. pin suspend will remain low in all other states. 0 softct softconnect: logic 1 enables the connection of the 1.5 k w pull-up resistor on pin rpu to the dp line. bus reset value: unchanged. table 21: mode register: bit description continued bit symbol description
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 27 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. if otg is logic 0, the status of the pull-up resistor on dp is referred to in ta b l e 2 2 . 9.2.3 interrupt con?guration register (address: 10h) this 1-byte register determines the behavior and polarity of the int output. the bit allocation is shown in ta b l e 2 3 . when the usb sie receives or generates an ack, nak or stall, it will generate interrupts depending on three debug mode ?elds. cdbgmod[1:0] interrupts for the control endpoint 0 ddbgmodin[1:0] interrupts for the data in endpoints 1 to 7 ddbgmodout[1:0] interrupts for the data out endpoints 1 to 7. the debug mode settings for cdbgmod, ddbgmodin and ddbgmodout allow you to individually con?gure when the ISP1582 sends an interrupt to the external microprocessor. ta b l e 2 5 lists the available combinations. bit intpol controls the signal polarity of the int output: active high or low, rising or falling edge. for level-triggering, bit intlvl must be made logic 0. by setting intlvl to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering). table 22: status of the chip v bus softconnect = on softconnect = off on pull-up resistor on dp pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals off pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals pull-up resistor on dp is removed; suspend interrupt is immediately set, regardless of the d+ and d - signals table 23: interrupt con?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol cdbgmod[1:0] ddbgmodin[1:0] ddbgmodout[1:0] intlvl intpol reset 11111100 bus reset 111111 unchanged unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 24: interrupt con?guration register: bit description bit symbol description 7 to 6 cdbgmod[1:0] control 0 debug mode: for values, see ta bl e 2 5 5 to 4 ddbgmodin[1:0] data debug mode in: for values, see ta b l e 2 5 3 to 2 ddbgmodout[1:0] data debug mode out: for values, see ta b l e 2 5 1 intlvl interrupt level : selects signaling mode on output int (0 = level; 1 = pulsed). in pulsed mode, an interrupt produces a 60 ns pulse. bus reset value: unchanged. 0 intpol interrupt polarity: selects signal polarity on output int (0 = active low; 1 = active high). bus reset value: unchanged.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 28 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] first nak: the ?rst nak on an in or out token after a previous ack response. 9.2.4 otg register (address: 12h) the bit allocation of the otg register is given in ta b l e 2 6 . table 25: debug mode settings value cdbgmod ddbgmodin ddbgmodout 00h interrupt on all ack and nak interrupt on all ack and nak interrupt on all ack, nyet and nak 01h interrupt on all ack. interrupt on ack interrupt on ack and nyet 1xh interrupt on all ack and ?rst nak [1] interrupt on all ack and ?rst nak [1] interrupt on all ack, nyet and ?rst nak [1] table 26: otg register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved dp bsessvalid initcond discv vp otg reset --0- -000 bus reset --0- -000 access - - r/w r/w r/w r/w r/w r/w table 27: otg register: bit description [1][2][3] bit symbol description 7 to 6 - reserved 5 dp when set, data-line pulsing is started. the default value of this bit is logic 0. this bit must be cleared when data-line pulsing is completed. 4 bsess valid the device can initiate another v bus discharge sequence after data-line pulsing and v bus pulsing, and before it clears this bit and detects a session valid. this bit is latched to logic 1 once v bus exceeds the b-device session valid threshold. once set, it remains at logic 1. to clear this bit, write logic 1. (the ISP1582 continuously updates this bit to logic 1 when the b-session is valid. if the b-session is valid after it is cleared, it is set back to logic 1 by the ISP1582). 0 it implies that srp has failed. to proceed to a normal operation, the device can restart srp, clear bit otg or proceed to an error handling process. 1 it implies that the b-session is valid. the device clears bit otg, goes into normal operation mode, and sets bit softct (dp pull-up) in the mode register. the otg host has a maximum of 5 s before it responds to a session request. during this period, the ISP1582 may request to suspend. therefore, the device ?rmware must wait for sometime if it wishes to know the srp result (successif there is minimum response from the host within 5 s; failureif there is no response from the host within 5 s).
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 29 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] no interrupt is designed for otg. the v bus interrupt, however, may assert as a side effect during the v bus pulsing (see note 2). [2] when otg is in progress, the v bus interrupt may be set because v bus is charged over v bus sensing threshold or the otg host has turned on the v bus supply to the device. even if the v bus interrupt is found during srp, the device should complete data-line pulsing and v bus pulsing before starting the b_session_valid detection. [3] otg implementation applies to the device with self-power capability. if the device works in sharing mode, it should provide a switch circuit to supply power to the ISP1582 core during srp. session request protocol (srp): the ISP1582 can initiate an srp. the b-device initiates srp by data-line pulsing followed by v bus pulsing. the a-device can detect either data-line pulsing or v bus pulsing. the ISP1582 can initiate the b-device srp by performing the following steps: 1. detect initial conditions: read bit initcond of the otg register. 2. start data-line pulsing: set bit dp of the otg register to logic 1. 3. wait for 5 ms to 10 ms. 4. stop data-line pulsing: set bit dp of the otg register to logic 0. 5. start v bus pulsing: set bit vp of the otg register to logic 1. 6. wait for 10 ms to 20 ms. 7. stop v bus pulsing: set bit vp of the otg register to logic 0. 8. discharge v bus for about 30 ms: optional by using bit discv of the otg register. 3 init cond write logic 1 to clear this bit. the device clears this bit, and waits for more than 2 ms to check the bit status. if it reads logic 0, it means that v bus remains lower than 0.8 v, and dp or dm at se0 during the elapsed time is cleared. the device can then start a b-device srp. if it reads logic 1, it means that the initial condition of an srp is violated. so, the device should abort srp. the bit is set to logic 1 by the ISP1582 when initial conditions are not met, and only writing logic 1 clears the bit. (if initial conditions are not met after this bit has been cleared, it will be set again). remark: this implementation does not cover the case if an initial srp condition is violated when this bit is read and data-line pulsing is started. 2 discv set to logic 1 to discharge v bus . the device discharges v bus before starting a new srp. the discharge can take as long as 30 ms for v bus to be charged less than 0.8 v. this bit must be cleared (write logic 0) before starting a session end detection. 1 vp set to logic 1 to start v bus pulsing. this bit must be set for more than 16 ms and must be cleared before 26 ms. 0otg 1 enables the otg function. the v bus sensing functionality will be bypassed. 0 normal operation. all otg control bits will be masked. status bits are unde?ned. table 27: otg register: bit description [1][2][3] continued bit symbol description
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 30 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. detect bit bsessvalid of the otg register for a successful srp with bit otg disabled. the b-device must complete both data-line pulsing and v bus pulsing within 100 ms. remark: when disabling, otg data-line pulsing bit dp and v bus pulsing bit vp must be cleared by writing logic 1. 9.2.5 interrupt enable register (address: 14h) this register enables or disables individual interrupt sources. the interrupt for each endpoint can be individually controlled via the associated bits iepnrx or iepntx, here n represents the endpoint number. all interrupts can be globally disabled through bit glintena in the mode register (see ta b l e 2 0 ). an interrupt is generated when the usb sie receives or generates an ack or nak on the usb bus. the interrupt generation depends on debug mode settings of bit ?elds cdbgmod[1:0], ddbgmodin[1:0] and ddbgmodout[1:0]. all data in transactions use the transmit buffers (tx), which are handled by bits ddbgmodin. all data out transactions go via the receive buffers (rx), which are handled by bits ddbgmodout. transactions on control endpoint 0 (in, out and setup) are handled by bits cdbgmod. interrupts caused by events on the usb bus (sof, pseudo sof, suspend, resume, bus reset, setup and high-speed status) can also be individually controlled. a bus reset disables all enabled interrupts except bit iebrst (bus reset), which remains unchanged. the interrupt enable register consists of 4 bytes. the bit allocation is given in ta b l e 2 8 . table 28: interrupt enable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved iep7tx iep7rx reset ------00 bus reset ------00 access - - - - - - r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep6tx iep6rx iep5tx iep5rx iep4tx iep4rx iep3tx iep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep2tx iep2rx iep1tx iep1rx iep0tx iep0rx reserved iep0setup reset 000000- 0 bus reset 000000- 0 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 31 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3 data ?ow registers 9.3.1 endpoint index register (address: 2ch) the endpoint index register selects a target endpoint for register access by the microcontroller. the register consists of 1 byte, and the bit allocation is shown in ta b l e 3 0 . bit 7 6 5 4 3 2 1 0 symbol ievbus iedma iehs_sta ieresm iesusp iepsof iesof iebrst reset 00000000 bus reset 0000000 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 29: interrupt enable register: bit description bit symbol description 31 to 26 - reserved 25 ep7tx logic 1 enables interrupt from the indicated endpoint. 24 ep7rx logic 1 enables interrupt from the indicated endpoint. 23 ep6tx logic 1 enables interrupt from the indicated endpoint. 22 ep6rx logic 1 enables interrupt from the indicated endpoint. 21 ep5tx logic 1 enables interrupt from the indicated endpoint. 20 ep5rx logic 1 enables interrupt from the indicated endpoint. 19 ep4tx logic 1 enables interrupt from the indicated endpoint. 18 ep4rx logic 1 enables interrupt from the indicated endpoint. 17 ep3tx logic 1 enables interrupt from the indicated endpoint. 16 ep3rx logic 1 enables interrupt from the indicated endpoint. 15 ep2tx logic 1 enables interrupt from the indicated endpoint. 14 ep2rx logic 1 enables interrupt from the indicated endpoint. 13 ep1tx logic 1 enables interrupt from the indicated endpoint. 12 iep1rx logic 1 enables interrupt from the indicated endpoint. 11 iep0tx logic 1 enables interrupt from the control in endpoint 0. 10 iep0rx logic 1 enables interrupt from the control out endpoint 0. 9 - reserved 8 iep0setup logic 1 enables interrupt for the setup data received on endpoint 0. 7 ievbus logic 1 enables interrupt for v bus sensing. 6 iedma logic 1 enables interrupt on dma status change detection. 5 iehs_sta logic 1 enables interrupt on detection of a high-speed status change. 4 ieresm logic 1 enables interrupt on detection of a resume state. 3 iesusp logic 1 enables interrupt on detection of a suspend state. 2 iepsof logic 1 enables interrupt on detection of a pseudo sof. 1 iesof logic 1 enables interrupt on detection of an sof. 0 iebrst logic 1 enables interrupt on detection of a bus reset.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 32 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following registers are indexed: ? buffer length ? buffer status ? control function ? data port ? endpoint maxpacketsize ? endpoint type. for example, to access the out data buffer of endpoint 1 using the data port register, the endpoint index register has to be written ?rst with 02h. remark: the endpoint index register and the dma endpoint index register must not point to the same endpoint. table 30: endpoint index register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved ep0setup endpidx[3:0] dir reset - - 000000 bus reset - - 000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 31: endpoint index register: bit description bit symbol description 7 to 6 - reserved 5 ep0setup selects the setup buffer for endpoint 0. 0 ep0 data buffer 1 setup buffer. must be logic 0 for access to other endpoints than endpoint 0. 4 to 1 endpidx[3:0] endpoint index: selects the target endpoint for register access of buffer length, control function, data port, endpoint type and maxpacketsize. 0 dir direction bit: sets the target endpoint as in or out. 0 target endpoint refers to out (rx) fifo 1 target endpoint refers to in (tx) fifo. table 32: addressing of endpoint 0 buffers buffer name ep0setup endpidx dir setup 1 00h 0 data out 0 00h 0 data in 0 00h 1
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 33 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.2 control function register (address: 28h) the control function register performs the buffer management on endpoints. it consists of 1 byte, and the bit con?guration is given in ta b l e 3 3 . the register bits can stall, clear or validate any enabled data endpoint. before accessing this register, the endpoint index register must be written ?rst to specify the target endpoint. 9.3.3 data port register (address: 20h) this 2-byte register provides direct access for a microcontroller to the fifo of the indexed endpoint. the bit allocation is shown in ta b l e 3 5 . table 33: control function register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved clbuf vendp dsen status stall reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 34: control function register: bit description bit symbol description 7 to 5 - reserved 4 clbuf clear buffer: logic 1 clears the rx buffer of the indexed endpoint; the tx buffer is not affected. the rx buffer is automatically cleared once the endpoint is completely read. this bit is set only when it is necessary to forcefully clear the buffer. 3 vendp validate endpoint: logic 1 validates the data in the tx fifo of an in endpoint for sending on the next in token. in general, the endpoint is automatically validated when its fifo byte count has reached the endpoint maxpacketsize. this bit is set only when it is necessary to validate the endpoint with the fifo byte count which is below the endpoint maxpacketsize. 2 dsen data stage enable : this bit controls the response of the ISP1582 to a control transfer. when this bit is set, the ISP1582 goes to the data stage; otherwise, the ISP1582 will nak the data stage transfer until the ?rmware explicitly responds to the setup command. 1 status status acknowledge: only applicable for control in/out. this bit controls the generation of ack or nak during the status stage of a setup transfer. it is automatically cleared when the status stage is completed, or when a setup token is received. no interrupt signal will be generated. 0 sends nak 1 sends an empty packet following the in token (host-to-peripheral) or ack following the out token (peripheral-to-host). 0 stall stall endpoint : logic 1 stalls the indexed endpoint. this bit is not applicable for isochronous transfers. remark: stalling a data endpoint will confuse the data toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. therefore, the data toggle bit must be reset by disabling and reenabling the corresponding endpoint (by setting bit enable to logic 0 or logic 1 in the endpoint type register) to reset the pid.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 34 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. peripheral-to-host (in endpoint): after each write action, an internal counter is auto incremented by two to the next location in the tx fifo. when all bytes have been written (fifo byte count = endpoint maxpacketsize), the buffer is automatically validated. the data packet will then be sent on the next in token. when it is necessary to validate the endpoint whose byte count is less than maxpacketsize, it can be done using the control function register (bit vendp). host-to-peripheral (out endpoint) : after each read action, an internal counter is auto decremented by two to the next location in the rx fifo. when all bytes have been read, the buffer contents are automatically cleared. a new data packet can then be received on the next out token. the buffer contents can also be cleared through the control function register (bit clbuf), when it is necessary to forcefully clear the contents. remark: the buffer can be automatically validated or cleared by using the buffer length register (see ta b l e 3 7 ). 9.3.4 buffer length register (address: 1ch) this register determines the current packet size (datacount) of the indexed endpoint fifo. the bit allocation is given in ta b l e 3 7 . the buffer length register is automatically loaded with the fifo size, when the endpoint maxpacketsize register is written (see ta b l e 4 1 ). a smaller value can be written when required. after a bus reset, the buffer length register is made zero. in endpoint: when data transfer is performed in multiples of maxpacketsize, the buffer length register is not signi?cant. this register is useful only when transferring data that is not a multiple of maxpacketsize. the following two examples demonstrate the signi?cance of the buffer length register. table 35: data port register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dataport[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dataport[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 36: data port register: bit description bit symbol description 15 to 8 dataport[15:8] data (upper byte) 7 to 0 dataport[7:0] data (lower byte)
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 35 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. example 1: consider that the transfer size is 512 bytes and the maxpacketsize is programmed as 64 bytes, the buffer length register need not be ?lled. this is because the transfer size is a multiple of maxpacketsize, and the maxpacketsize packets will be automatically validated because the last packet is also of maxpacketsize. example 2: consider that the transfer size is 510 bytes and the maxpacketsize is programmed as 64 bytes, the buffer length register should be ?lled with 62 bytes just before the mcu writes the last packet of 62 bytes. this ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. use bit vendp in the control register if you are not using the buffer length register. this is applicable only to pio mode access. out endpoint: the datacount value is automatically initialized to the number of data bytes sent by the host on each ack. remark: when using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (lsbyte). remark: buffer length is valid only after an interrupt is generated for the bulk endpoint. 9.3.5 buffer status register (address: 1eh) this register is accessed using index. the endpoint index must ?rst be set before accessing this register for the corresponding endpoint. it re?ects the status of the double buffered endpoint fifo. this register is valid only when the endpoint is con?gured to be a double buffer. remark: this register is not applicable to the control endpoint. ta b l e 3 9 shows the bit allocation of the buffer status register. table 37: buffer length register: bit allocation bit 15 14 13 12 11 10 9 8 symbol datacount[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol datacount[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 38: buffer length register: bit description bit symbol description 15 to 0 datacount[15:0] determines the current packet size of the indexed endpoint fifo.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 36 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3.6 endpoint maxpacketsize register (address: 04h) this register determines the maximum packet size for all endpoints except control 0. the register contains 2 bytes, and the bit allocation is given in ta b l e 4 1 . each time the register is written, the buffer length registers of all endpoints are reinitialized to the ffosz ?eld value. bits ntrans control the number of transactions allowed in a single microframe (for high-speed isochronous and interrupt endpoints only). table 39: buffer status register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved buf1 buf0 reset ------00 bus reset ------00 access ------rr table 40: buffer status register: bit description bit symbol description 7 to 2 - reserved 1 to 0 buf[1:0] 00 the buffers are not ?lled. 01 one of the buffers is ?lled. 10 one of the buffers is ?lled. 11 both the buffers are ?lled. table 41: endpoint maxpacketsize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved ntrans[1:0] ffosz[10:8] reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ffosz[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 37 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. each programmable fifo can be independently con?gured via its endpoint maxpacketsize register (r/w: 04h), but the total physical size of all enabled endpoints (in plus out) must not exceed 8192 bytes. 9.3.7 endpoint type register (address: 08h) this register sets the endpoint type of the indexed endpoint: isochronous, bulk or interrupt. it also serves to enable the endpoint and con?gure it for double buffering. automatic generation of an empty packet for a zero-length tx buffer can be disabled using bit noempkt. the register contains 2 bytes, and the bit allocation is shown in ta b l e 4 4 . table 42: endpoint maxpacketsize register: bit description bit symbol description 15 to 13 - reserved 12 to 11 ntrans[1:0] number of transactions . hs mode only. 00 1 packet per microframe 01 2 packets per microframe 10 3 packets per microframe 11 reserved. these bits are applicable only for isochronous or interrupt transactions. 10 to 0 ffosz[10:0] fifo size : sets the fifo size, in bytes, for the indexed endpoint. applies to both high-speed and full-speed operations (see ta b l e 4 3 ). table 43: programmable fifo size ntrans[1:0] ffosz[10:0] non-isochronous isochronous 0h 08h 8 bytes - 0h 10h 16 bytes - 0h 20h 32 bytes - 0h 40h 64 bytes - 0h 80h 128 bytes - 0h 100h 256 bytes - 0h 200h 512 bytes - 2h 400h - 3072 bytes table 44: endpoint type register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- bus reset -------- access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 38 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 dma registers the generic dma (gdma) transfer can be done by writing the proper opcode in the dma command register. the control bits are given in ta b l e 4 6 . gdma read/write (opcode = 00h/01h) for generic dma slave mode depending on the mode[1:0] bit set in the dma con?guration register, either the dack signal or the dior/diow signals strobe the data. these signals are driven by the external dma controller. gdma (slave) mode can operate in either counter mode or eot-only mode. in counter mode, bit dis_xfer_cnt in the dma con?guration register must be set to logic 0. the dma transfer counter register must be programmed before any dma command is issued. the dma transfer counter is set by writing from the lsbyte to the msbyte (address: 34h to 37h). the dma transfer count is internally updated only after the msbyte has been written. once the dma transfer is started, the transfer counter starts decrementing and on reaching 0, bit dma_xfer_ok is set and an bit 7 6 5 4 3 2 1 0 symbol reserved noempkt enable dblbuf endptyp[1:0] reset - - - 00000 bus reset - - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 45: endpoint type register: bit description bit symbol description 15 to 5 - reserved 4 noempkt no empty packet: logic 0 causes the ISP1582 to return a null length packet for the in token after the dma in transfer is complete. for ata mode or the in dma transfer, which does not require a null length packet after dma completion, set to logic 1 to disable the generation of the null length packet. 3 enable endpoint enable : logic 1 enables the fifo of the indexed endpoint. the memory size is allocated as speci?ed in the endpoint maxpacketsize register. logic 0 disables the fifo. remark: stalling a data endpoint will confuse the data toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. therefore, the data toggle bit must be reset by disabling and reenabling the corresponding endpoint (by setting bit enable to logic 0 or logic 1 in the endpoint type register) to reset the pid. 2 dblbuf double buffering: logic 1 enables double buffering for the indexed endpoint. logic 0 disables double buffering. 1 to 0 endptyp[1:0] endpoint type: these bits select the endpoint type as follows. 00 not used 01 isochronous 10 bulk 11 interrupt.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 39 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. interrupt is generated by the ISP1582. if the dma master wishes to terminate the dma transfer, it can issue an eot signal to the ISP1582. this eot signal overrides the transfer counter and can terminate the dma transfer at any time. in eot-only mode, dis_xfer_cnt has to be set to logic 1. although the dma transfer counter can still be programmed, it will not have any effect on the dma transfer. the dma transfer will start once the dma command is issued. any of the following three ways will terminate this dma transfer: ? detecting an external eot ? detecting an internal eot (short packet on an out token) ? resetting the dma. there are three interrupts programmable to differentiate the method of dma termination: bits int_eot, ext_eot and dma_xfer_ok in the dma interrupt reason register. for details, see ta b l e 5 8 . remark: the dma bus defaults to three-state, until a dma command is executed. all the other control signals are not three-state. 9.4.1 dma command register (address: 30h) the dma command register is a 1-byte register (for bit allocation, see ta b l e 4 7 ) that initiates all dma transfer activity on the dma controller. the register is write-only: reading it will return ffh. remark: the dma bus will be in three-state until a dma command is executed. table 46: control bits for gdma read/write (opcode = 00h/01h) control bits description reference dma con?guration register mode[1:0] determines the active read/write data strobe signals. ta b l e 5 2 width selects the dma bus width: 8 or 16 bits. dis_xfer_cnt disables the use of the dma transfer counter. dma hardware register eot_pol selects the polarity of the eot signal. ta b l e 5 4 endian[1:0] determines whether the data is to be byte swapped or normal. applicable only in 16-bit mode. ack_pol, dreq_pol, write_pol, read_pol select the polarity of the dma handshake signals. table 47: dma command register: bit allocation bit 7 6 5 4 3 2 1 0 symbol dma_cmd[7:0] reset 11111111 bus reset 11111111 access wwwwwwww
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 40 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.2 dma transfer counter register (address: 34h) this 4-byte register sets up the total byte count for a dma transfer (dmacr). it indicates the remaining number of bytes left for transfer. the bit allocation is given in ta b l e 5 0 . for in endpoint as there is a fifo in the ISP1582 dma controller, some data may remain in the fifo during the dma transfer. the maximum fifo size is 8 bytes, and the maximum delay time for the data to be shifted to endpoint buffer is 60 ns. for out endpoint data will not be cleared for the endpoint buffer until all the data has been read from the dma fifo. if the dma counter is disabled in the dma transfer, it will still decrement and rollover when it reaches zero. table 48: dma command register: bit description bit symbol description 7 to 0 dma_cmd[7:0] dma command code; see ta bl e 4 9 . table 49: dma commands code name description 00h gdma read generic dma in token transfer (slave mode only): data is transferred from the external dma bus to the internal buffer. strobe: diow by external dma controller. 01h gdma write generic dma out token transfer (slave mode only): data is transferred from the internal buffer to the external dma bus. strobe: dior by external dma controller. 02h to 0dh - reserved 0eh validate buffer validate buffer (for debugging only): request from the microcontroller to validate the endpoint buffer following a dma to usb data transfer. 0fh clear buffer clear buffer: request from the microcontroller to clear the endpoint buffer after a usb to dma data transfer. 10h - reserved 11h reset dma reset dma: initializes the dma core to its power-on reset state. remark: when the dma core is reset during the reset dma command, the dreq, dack, diow and dior handshake pins will be temporarily asserted. this can confuse the external dma controller. to prevent this, start the external dma controller only after the dma reset. 12h - reserved 13h gdma stop gdma stop : this command stops the gdma data transfer. any data in the out endpoint that is not transferred by the dma will remain in the buffer. the fifo data for the in endpoint will be written to the endpoint buffer. an interrupt bit will be set to indicate the completion of the dma stop command. 14h to ffh - reserved table 50: dma transfer counter register: bit allocation bit 31 30 29 28 27 26 25 24 symbol dmacr4 = dmacr[31:24] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 41 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.3 dma con?guration register (address: 38h) this register de?nes the dma con?guration for gdma mode. the dma con?guration register consists of 2 bytes. the bit allocation is given in ta b l e 5 2 . bit 23 22 21 20 19 18 17 16 symbol dmacr3 = dmacr[23:16] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dmacr2 = dmacr[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr1 = dmacr[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 51: dma transfer counter register: bit description bit symbol description 31 to 24 dmacr4, dmacr[31:24] dma transfer counter byte 4 (msb) 23 to 16 dmacr3, dmacr[23:16] dma transfer counter byte 3 15 to 8 dmacr2, dmacr[15:8] dma transfer counter byte 2 7 to 0 dmacr1, dmacr[7:0] dma transfer counter byte 1 (lsb) table 52: dma con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dis_ xfer_cnt reserved mode[1:0] reserved width reset 00000001 bus reset 00000001 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 42 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the dreq pin will only be driven only after you perform a write access to the dma con?guration register (that is, after you have con?gured the dma con?guration register). 9.4.4 dma hardware register (address: 3ch) the dma hardware register consists of 1 byte. the bit allocation is shown in ta b l e 5 4 . this register determines the polarity of the bus control signals (eot, dack, dreq, dior and diow) and dma mode (master or slave). it also controls whether the upper and lower parts of the data bus are swapped (bits endian[1:0]) for gdma (slave) mode. table 53: dma con?guration register: bit description [1] bit symbol description 15 to 8 - reserved 7 dis_xfer_cnt logic 1 disables the dma transfer counter (see ta b l e 5 0 ). the transfer counter can be disabled only in gdma (slave) mode. 6 to 4 - reserved 3 to 2 mode[1:0] these bits only affect the gdma slave handshake signals. 00 diow slave strobes data from the dma bus into the ISP1582; dior slave puts data from the ISP1582 on the dma bus 01 dack slave strobes data from the dma bus into the ISP1582; dior slave puts data from the ISP1582 on the dma bus 10 dack slave strobes data from the dma bus into the ISP1582 and also puts data from the ISP1582 on the dma bus. (this mode is applicable only to the 16-bit dma; this mode cannot be used for the 8-bit dma.) 11 reserved. 1 - reserved 0 width this bit selects the dma bus width for the gdma slave. 0 8-bit data bus 1 16-bit data bus. table 54: dma hardware register: bit allocation bit 7 6 5 4 3 2 1 0 symbol endian[1:0] eot_pol reserved ack_pol dreq_ pol write_ pol read_ pol reset 00000100 bus reset 00000100 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 43 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4.5 dma interrupt reason register (address: 50h) this 2-byte register shows the source(s) of dma interrupt. each bit is refreshed after a dma command has been executed. an interrupt source is cleared by writing logic 1 to the corresponding bit. when reading, and the value of the bits in this register with the value of the corresponding bits in the dma interrupt enable register. the bit allocation is given in ta b l e 5 6 . table 55: dma hardware register: bit description bit symbol description 7 to 6 endian[1:0] these bits determine whether the data bus is swapped between the internal ram and the dma bus. this only applies for gdma (slave) mode. 00 normal data representation 16-bit bus: msb on data[15:8], lsb on data[7:0] 01 swapped data representation 16-bit bus: msb on data[7:0], lsb on data[15:8] 10 reserved 11 reserved. remark: while operating with the 8-bit data bus, bits endian[1:0] should be always set to logic 00. 5 eot_pol selects the polarity of the end-of-transfer input; used in gdma (slave) mode only. 0 eot is active low 1 eot is active high. 4 - reserved; must be set to logic 0. 3 ack_pol selects the dma acknowledgment polarity. 0 dack is active low 1 dack is active high. 2 dreq_pol selects the dma request polarity. 0 dreq is active low 1 dreq is active high. 1 write_pol selects the diow strobe polarity. 0 diow is active low 1 diow is active high. 0 read_pol selects the dior strobe polarity. 0 dior is active low 1 dior is active high.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 44 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. ta b l e 5 9 shows the status of the bits in the dma interrupt reason register when the corresponding bits in the interrupt register is set. table 56: dma interrupt reason register: bit allocation bit 15 14 13 12 11 10 9 8 symbol test3 reserved gdma_ stop ext_eot int_eot reserved dma_ xfer_ok reset ---000-0 bus reset ---000-0 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved reset -------- bus reset -------- access r/w r/w r/w r/w r/w r/w r/w r/w table 57: dma interrupt reason register: bit description bit symbol description 15 test3 this bit is set when the dma transfer for a packet (out transfer) terminates before the whole packet has been transferred. this bit is a status bit, and the corresponding mask bit of this register is always logic 0. writing any value other than logic 0 has no effect. 14 to 13 - reserved 12 gdma_stop when the gdma_stop command is issued to the dma command registers, it means the dma transfer has successfully terminated. 11 ext_eot logic 1 indicates that an external eot is detected. this is applicable only in gdma (slave) mode. 10 int_eot logic 1 indicates that an internal eot is detected; see ta bl e 5 8 . 9 - reserved 8 dma_xfer_ok logic 1 indicates that the dma transfer has been completed (dma transfer counter has become zero). this bit is only used in gdma (slave) mode. 7 to 0 - reserved table 58: internal eot-functional relation with bit dma_xfer_ok int_eot dma_xfer_ok description 1 0 during the dma transfer, there is a premature termination with short packet. 1 1 dma transfer is completed with short packet and the dma transfer counter has reached 0. 0 1 dma transfer is completed without any short packet and the dma transfer counter has reached 0.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 45 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] 1 indicates that the bit is set and 0 indicates that the bit is not set. a bit is set when the corresponding eot condition is met. for example; ext_eot is set if external eot conditions are met (pin eot active), regardless of other eot conditions. if multiple eot conditions are met, the corresponding interrupt bits are set. [2] if both ext_eot and dma_xfer_ok conditions are met in dma for an in endpoint, the ext_eot interrupt is not set. [3] the value of int_eot may not be accurate if an external or internal transfer counter is programmed with a value that is lower than the transfer that the host requests. to terminate an out transfer with int_eot, the external or internal dma counter should be programmed as a multiple of the full-packet length of the dma endpoint. when a short packet is successfully transferred by dma, int_eot is set. 9.4.6 dma interrupt enable register (address: 54h) this 2-byte register controls the interrupt generation of the source bits in the dma interrupt reason register. the bit allocation is given in ta b l e 6 0 . the bit description is given in ta b l e 5 7 . logic 1 enables the interrupt generation. after a bus reset, interrupt generation is disabled, with the values turning to logic 0. 9.4.7 dma endpoint register (address: 58h) this 1-byte register selects a usb endpoint fifo as a source or destination for dma transfers. the bit allocation is given in ta b l e 6 1 . table 59: status of the bits in the dma interrupt reason register [1][2] status ext_eot int_eot dma_xfer_ok counter enabled counter disabled in full 1 0 1 0 in short 1 0 1 0 out full 1 0 1 0 out short 1 1 [3] 10 table 60: dma interrupt enable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol test4 reserved ie_gdma_ stop ie_ext_ eot ie_int_ eot reserved ie_dma_ xfer_ok reset - - - 00000 bus reset - - - 00000 access r - - r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 61: dma endpoint register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved epidx[2:0] dmadir reset ---- 0000 bus reset ---- 0000 access ----r/wr/wr/wr/w
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 46 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. the dma endpoint register must not reference the endpoint that is indexed by the endpoint index register (2ch) at any time. doing so would result in data corruption. therefore, if the dma endpoint register is unused, point it to an unused endpoint. if the dma endpoint register, however, is pointed to an active endpoint, the ?rmware must not reference the same endpoint on the endpoint index register. 9.4.8 dma burst counter register (address: 64h) ta b l e 6 3 shows the bit allocation of the register. 9.5 general registers 9.5.1 interrupt register (address: 18h) the interrupt register consists of 4 bytes. the bit allocation is given in ta b l e 6 5 . table 62: dma endpoint register: bit description bit symbol description 7 to 4 - reserved 3 to 1 epidx[2:0] selects the indicated endpoint for dma access 0 dmadir 0 selects the rx/out fifo for dma read transfers 1 selects the tx/in fifo for dma write transfers. table 63: dma burst counter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved burstcounter[12:8] reset - - - 00000 bus reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol burstcounter[7:0] reset 00000010 bus reset 00000010 access r/w r/w r/w r/w r/w r/w r/w r/w table 64: dma burst counter register: bit description bit symbol description 15 to 13 - reserved 12 to 0 burstcounter[12:0] this register de?nes the burst length. the counter must be programmed to be a multiple of two in 16-bit mode. the value of the burst counter should be programmed such that the buffer counter is a factor of the burst counter. for in endpoint when the burst counter equals 2, in gdma mode, dreq will drop at every dma read or write cycle.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 47 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. when a bit is set in the interrupt register, it indicates that the hardware condition for an interrupt has occurred. when the interrupt register content is nonzero, the int output will be asserted corresponding to the interrupt enable register. on detecting the interrupt, the external microprocessor must read the interrupt register and mask it with the corresponding bits in the interrupt enable register to determine the source of the interrupt. each endpoint buffer has a dedicated interrupt bit (epntx, epnrx). in addition, various bus states can generate an interrupt: resume, suspend, pseudo sof, sof and bus reset. the dma controller only has one interrupt bit: the source for a dma interrupt is shown in the dma interrupt reason register. each interrupt bit can be individually cleared by writing logic 1. the dma interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the dma interrupt reason register and writing logic 1 to the dma bit of the interrupt register. table 65: interrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved ep7tx ep7rx reset -----000 bus reset -----000 access -----r/wr/wr/w bit 23 22 21 20 19 18 17 16 symbol ep6tx ep6rx ep5tx ep5rx ep4tx ep4rx ep3tx ep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ep2tx ep2rx ep1tx ep1rx ep0tx ep0rx reserved ep0setup reset 000000- 0 bus reset 000000- 0 access r/w r/w r/w r/w r/w r/w - r/w bit 7 6 5 4 3 2 1 0 symbol vbus dma hs_stat resume susp psof sof breset reset 00000000 bus reset 0000000 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 66: interrupt register: bit description bit symbol description 31 to 26 - reserved 25 ep7tx logic 1 indicates the endpoint 7 tx buffer as interrupt source. 24 ep7rx logic 1 indicates the endpoint 7 rx buffer as interrupt source. 23 ep6tx logic 1 indicates the endpoint 6 tx buffer as interrupt source. 22 ep6rx logic 1 indicates the endpoint 6 rx buffer as interrupt source. 21 ep5tx logic 1 indicates the endpoint 5 tx buffer as interrupt source.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 48 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.2 chip id register (address: 70h) this read-only register contains the chip identi?cation and the hardware version numbers. the ?rmware should check this information to determine the functions and features supported. the register contains 3 bytes, and the bit allocation is shown in ta b l e 6 7 . 20 ep5rx logic 1 indicates the endpoint 5 rx buffer as interrupt source. 19 ep4tx logic 1 indicates the endpoint 4 tx buffer as interrupt source. 18 ep4rx logic 1 indicates the endpoint 4 rx buffer as interrupt source. 17 ep3tx logic 1 indicates the endpoint 3 tx buffer as interrupt source. 16 ep3rx logic 1 indicates the endpoint 3 rx buffer as interrupt source. 15 ep2tx logic 1 indicates the endpoint 2 tx buffer as interrupt source. 14 ep2rx logic 1 indicates the endpoint 2 rx buffer as interrupt source. 13 ep1tx logic 1 indicates the endpoint 1 tx buffer as interrupt source. 12 ep1rx logic 1 indicates the endpoint 1 rx buffer as interrupt source. 11 ep0tx logic 1 indicates the endpoint 0 data tx buffer as interrupt source. 10 ep0rx logic 1 indicates the endpoint 0 data rx buffer as interrupt source. 9 - reserved 8 ep0setup logic 1 indicates that a setup token was received on endpoint 0. 7 vbus logic 1 indicates v bus is turned on. 6 dma dma status: logic 1 indicates a change in the dma status register. 5 hs_stat high speed status: logic 1 indicates a change from full-speed to high-speed mode (hs connection). this bit is not set, when the system goes into full-speed suspend. 4 resume resume status: logic 1 indicates that a status change from suspend to resume (active) was detected. 3 susp suspend status: logic 1 indicates that a status change from active to suspend was detected on the bus. 2 psof pseudo sof interrupt: logic 1 indicates that a pseudo sof or m sof was received. pseudo sof is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 m s period) synchronized to the usb bus sof or m sof. 1 sof sof interrupt: logic 1 indicates that a sof or m sof was received. 0 breset bus reset : logic 1 indicates that a usb bus reset was detected. when bit otg in the otg register is set, breset will not be set, instead, this interrupt bit will report se0 on dp and dm for 2 ms. table 66: interrupt register: bit description continued bit symbol description table 67: chip id register: bit allocation bit 23 22 21 20 19 18 17 16 symbol chipid[15:8] reset 00010101 bus reset 00010101 access rrrrrrrr
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 49 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.3 frame number register (address: 74h) this read-only register contains the frame number of the last successfully received start-of-frame (sof). the register contains 2 bytes, and the bit allocation is given in ta b l e 6 9 . in case of 8-bit access, the register content is returned lower byte ?rst. 9.5.4 scratch register (address: 78h) this 16-bit register can be used by the ?rmware to save and restore information. for example, the device status before it enters the suspend state. the bit allocation is given in ta b l e 7 1 . bit 15 14 13 12 11 10 9 8 symbol chipid[7:0] reset 10000010 bus reset 10000010 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol version[7:0] reset 00110000 bus reset 00110000 access rrrrrrrr table 68: chip id register: bit description bit symbol description 23 to 16 chipid[15:8] chip id: lower byte (15h) 15 to 8 chipid[7:0] chip id: upper byte (82h) 7 to 0 version[7:0] version number (30h) table 69: frame number register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved microsof[2:0] sofr[10:8] power reset - - 000000 bus reset - - 000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofr[7:0] power reset 00000000 bus reset 00000000 access rrrrrrrr table 70: frame number register: bit description bit symbol description 15 to 14 - reserved 13 to 11 microsof[2:0] microframe number 10 to 0 sofr[10:0] frame number
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 50 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.5.5 unlock device register (address: 7ch) to protect the registers from getting corrupted when the ISP1582 goes into suspend, the write operation is disabled if bit pwron in the mode register is set to logic 0. in this case, when the chip resumes, the unlock device command must be ?rst issued to this register before attempting to write to the rest of the registers. this is done by writing unlock code (aa37h) to this register. the bit allocation of the unlock device register is given in ta b l e 7 3 . when bit pwron in the mode register is logic 1, the chip is powered. in such a case, you do not need to issue the unlock command because the microprocessor is powered and therefore, the rd_n, wr_n and cs_n signals maintain their states. table 71: scratch register: bit allocation bit 15 14 13 12 11 10 9 8 symbol sfirh[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 72: scratch register: bit description bit symbol description 15 to 8 sfirh[7:0] scratch ?rmware information register (higher byte) 7 to 0 sfirl[7:0] scratch ?rmware information register (lower byte) table 73: unlock device register: bit allocation bit 15 14 13 12 11 10 9 8 symbol ulcode[15:8] = aah reset not applicable bus reset not applicable access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol ulcode[7:0] = 37h reset not applicable bus reset not applicable access wwwwwwww table 74: unlock device register: bit description bit symbol description 15 to 0 ulcode[15:0] writing data aa37h unlocks the internal registers and fifos for writing, following a resume.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 51 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. when bit pwron is logic 0, the rd_n, wr_n and cs_n signals are ?oating because the microprocessor is not powered. to protect the ISP1582 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. therefore, you need to issue the unlock command to unlock the ISP1582 registers. 9.5.6 test mode register (address: 84h) this 1-byte register allows the ?rmware to set pins dp and dm to predetermined states for testing purposes. the bit allocation is given in ta b l e 7 5 . remark: only one bit can be set to logic 1 at a time. this must be implemented for the hi-speed usb logo compliance testing. [1] either forcehs or forcefs should be set at a time. [2] of the four bits (prbs, kstate, jstate and se0_nak), only one bit should be set at a time. table 75: test mode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol forcehs reserved forcefs prbs kstate jstate se0_nak reset 0 - - 00000 bus reset 0 - - 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 76: test mode register: bit description bit symbol description 7 forcehs logic 1 [1] forces the hardware to high-speed mode only and disables the chirp detection logic. 6 to 5 - reserved. 4 forcefs logic 1 [1] forces the physical layer to full-speed mode only and disables the chirp detection logic. 3 prbs logic 1 [2] sets pins dp and dm to toggle in a predetermined random pattern. 2 kstate writing logic 1 [2] sets pins dp and dm to the k state. 1 jstate writing logic 1 [2] sets pins dp and dm to the j state. 0 se0_nak writing logic 1 [2] sets pins dp and dm to a high-speed quiescent state. the device only responds to a valid high-speed in token with a nak.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 52 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. limiting values [1] the maximum value for 5 v tolerant pins is 6 v. 11. recommended operating conditions table 77: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v v cc(i/o) i/o pad supply voltage - 0.5 +4.6 v v i input voltage [1] - 0.5 v cc + 0.5 v i lu latch-up current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <1 m a - 2000 +2000 v t stg storage temperature - 40 +125 c table 78: recommended operating conditions symbol parameter conditions min max unit v cc supply voltage 3.0 3.6 v v cc(i/o) i/o pad supply voltage v cc v cc v v i input voltage range v cc = 3.3 v 0 5.5 v v i(ai/o) input voltage on analog i/o pins dp and dm 0 3.6 v v o(pu) open-drain output pull-up voltage 0 v cc v t amb ambient temperature - 40 +85 c
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 53 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. static characteristics [1] this value is applicable to transistor input only. the value will be different if internal pull-up or pull-down resistors ar e used. table 79: static characteristics; supply pins v cc = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; typical values at t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply voltage v cc supply voltage 3.0 3.3 3.6 v i cc operating supply current v cc = 3.3 v high-speed - 45 60 ma full-speed - 17 25 ma i cc(susp) suspend supply current v cc = 3.3 v - 160 - m a i/o pad supply voltage v cc(i/o) i/o pad supply voltage v cc v cc v cc v i cc(i/o) operating supply current v cc(i/o) = 3.3 v high-speed - 430 500 m a full-speed - 180 120 m a i cc(i/o)(susp) suspend supply current v cc(i/o) = 3.3 v - 5 10 m a regulated supply voltage v cc(1v8) regulated supply voltage with voltage converter 1.65 1.8 1.95 v table 80: static characteristics: digital pins v cc(i/o) =v cc ; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.3v cc(i/o) v v ih high-level input voltage 0.7v cc(i/o) -- v output levels v ol low-level output voltage i ol = rated drive - - 0.15v cc(i/o) v v oh high-level output voltage i oh = rated drive 0.8v cc(i/o) -- v leakage current i li input leakage current [1] - 5- +5 m a table 81: static characteristics: otg detection v cc(i/o) =v cc ; v gnd =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit charging and discharging resistor r pd discharging resistor 684.8 843.5 1032 w r pu charging resistor 551.9 666.7 780.6 w comparator levels v bvalid v bus valid detection v cc(i/o) = 3.3 v 0.3 v 2.0 - 4.0 v v sesend v bus b-session end detection v cc(i/o) = 3.3 v 0.3 v 0.2 - 0.8 v
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 54 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] pin dp is the usb positive data pin and pin dm is the usb negative data pin. 13. dynamic characteristics table 82: static characteristics: analog i/o pins dp and dm [1] v cc = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(dp) - v i(dm) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v se single-ended receiver threshold 0.8 2.0 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt-trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage r l = 1.5 k w to 3.6 v - - 0.4 v v oh high-level output voltage r l =15k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current 0 < v i < 3.3 v - 10 - +10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance z drv driver output impedance steady-state drive 40.5 - 49.5 w z inp input impedance 10 - - m w table 83: dynamic characteristics v cc = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w(reset_n) pulse width on pin reset_n crystal oscillator running 500 - - m s crystal oscillator f xtal crystal frequency - 12 - mhz r s series resistance - - 100 w c l load capacitance - 18 - pf external clock input v in input voltage 1.65 1.8 1.95 v t j external clock jitter - - 500 ps d clock duty cycle 45 50 55 % t r , t f rise time and fall time - - 3 ns
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 55 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] excluding the ?rst transition from the idle state. [2] characterized only, not tested. limits guaranteed by design. table 84: dynamic characteristics: analog i/o pins dp and dm v cc = 3.3 v 0.3 v; v gnd =0v; t amb = - 40 cto+85 c; c l = 50 pf; r pu = 1.5 k w on dp to v term ; test circuit of figure 25 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics full-speed mode t fr rise time c l =50pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns frfm differential rise time and fall time matching (t fr /t ff ) [1] 90 - 111.11 % v crs output signal crossover voltage [1][2] 1.3 - 2.0 v high-speed mode t hsr high-speed differential rise time with captive cable 500 - - ps t hsf high-speed differential fall time with captive cable 500 - - ps data source timing full-speed mode t feopt source eop width see figure 16 [2] 160 - 175 ns t fdeop source differential data-to-eop transition skew see figure 16 [2] - 2 - +5 ns receiver timing full-speed mode t jr1 receiver data jitter tolerance to next transition see figure 17 [2] - 18.5 - +18.5 ns t jr2 receiver data jitter tolerance for paired transitions see figure 17 [2] - 9 - +9 ns t feopr receiver se0 width accepted as eop; see figure 16 [2] 82--ns t fst width of se0 during differential transition rejected as eop; see figure 18 [2] --14ns
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 56 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. t period is the bit duration corresponding with the usb data rate. full-speed timing symbols have a subscript pre?x f, low-speed timing symbols have a pre?x 'l'. fig 16. source differential data-to-eop transition skew and eop width. mgr776 t period differential data lines crossover point differential data to se0/eop skew n t period + t deop source eop width: t eopt receiver eop width: t eopr crossover point extended + 3.3 v 0 v t period is the bit duration corresponding with the usb data rate. fig 17. receiver differential data jitter. mgr871 t period t jr differential data lines + 3.3 v 0 v t jr1 t jr2 consecutive transitions n t period + t jr1 paired transitions n t period + t jr2 fig 18. receiver se0 width tolerance. mgr872 differential data lines + 3.3 v 0 v t fst v ih(min)
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 57 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.1 register access timing table 85: register access timing parameters: separate address and data buses v cc(i/o) =v cc = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit reading t rlrh rd_n low pulse width >t rldv -ns t avrl address set-up time before rd_n low 0 - ns t rhax address hold time after rd_n high 0 - ns t rldv rd_n low to data valid delay - 26 ns t rhdz rd_n high to data outputs three-state delay 0 15 ns t rhsh rd_n high to cs_n high delay 0 - ns t slrl cs_n low to rd_n low delay 2 - ns writing t wlwh wr_n low pulse width 15 - ns t avwl address set-up time before wr_n low 0 - ns t whax address hold time after wr_n high 0 - ns t dvwh data set-up time before wr_n high 11 - ns t whdz data hold time after wr_n high 5 - ns t whsh wr_n high to cs_n high delay 0 - ns t slwl cs_n low to wr_n low delay 2 - ns general t cy(rw) read/write cycle time 50 - ns fig 19. register access timing: separate address and data buses. (write) data [ 15:0 ] (read) data [ 15:0 ] 004aaa276 a [ 7:0 ] t whsh t avwl t dvwh t rhdz t avrl t cy(rw) t whax t rhax t rldv t whdz wr_n cs_n rd_n t rhsh t rlrh t wlwh t slwl t slrl
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 58 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13.2 dma timing table 86: gdma (slave) mode timing parameters v cc(i/o) =v cc = 3.3 v; v gnd =0v; t amb = - 40 cto+85 c. symbol parameter min max unit t cy1 read/write cycle time 75 - ns t su1 dreq set-up time before ?rst dack on 10 - ns t d1 dreq on delay after last strobe off 33.33 - ns t h1 dreq hold time after last strobe on 0 53 ns t w1 dior/diow pulse width 39 600 ns t w2 dior/diow recovery time 36 - ns t d2 read data valid delay after strobe on - 20 ns t h2 read data hold time after strobe off - 5 ns t h3 write data hold time after strobe off 1 - ns t su2 write data set-up time before strobe off 10 - ns t su3 dack set-up time before dior/diow assertion 0 - ns t a1 dack deassertion after dior/diow deassertion 0 30 ns dreq is continuously asserted until the last transfer is done or the fifo is full. data strobes: dior (read) and diow (write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 20. gdma (slave) mode timing (bits mode[1:0] = 00). t h1 t w1 t su1 t d1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) dack (1) dior/diow (1) mgt500 t su3 t w2 t a1 t h3
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 59 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. dreq is asserted for every transfer. data strobes: dior (read) and dack (write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 21. gdma (slave) mode timing (bits mode[1:0] = 01). t d1 t w1 t su1 t h1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) dack (1) dior/diow (1) mgt502 t su3 t a1 t h3 dreq is continuously asserted until the last transfer is done or the fifo is full. data strobe: dack (read/write). (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. fig 22. gdma (slave) mode timing (bits mode[1:0] = 10). t h1 t w1 t su1 t d1 t su2 t d2 t h2 t cy1 (write) data [ 15:0 ] (read) data [ 15:0 ] dreq (2) high dack (1) dior/diow (1) mgt501 t w2 t h3
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 60 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. application information 15. test information the dynamic characteristics of the analog i/o ports dp and dm were determined using the circuit shown in figure 25 . (1) programmable polarity: shown as active low. remark: eot should be valid for 36 ns (minimum) when rd_n/wr_n is active. fig 23. eot timing in generic processor mode. eot (1) rd_n, wr_n 004aaa378 36 ns (min) dreq t h1 fig 24. typical interface connections for generic processor mode. 004aaa206 data read strobe 16 ISP1582 cpu data[15:0] rd_n address 8 a[7:0] write strobe wr_n chip select cs_n in full-speed mode, an internal 1.5 k w pull-up resistor is connected to pin dp. fig 25. load impedance for pins dp and dm (full-speed mode). test point c l 50 pf 15 k w d.u.t mgt495
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 61 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. package outline fig 26. hvqfn56 package outline. 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm d h 4.45 4.15 y 1 4.45 4.15 e 1 6.5 e 2 6.5 0.30 0.18 0.05 0.00 8.1 7.9 8.1 7.9 0.05 0.1 dimensions (mm are the original dimensions) sot684-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot684-1 hvqfn56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 15 28 56 43 42 29 14 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 62 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. soldering 17.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 17.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 17.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 63 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 17.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 17.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 87: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors ISP1582 hi-speed usb peripheral controller preliminary data rev. 03 25 august 2004 64 of 66 9397 750 13699 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 18. revision history table 88: revision history rev date cpcn description 03 2004xxxx - preliminary data (9397 750 13699) modi?cations: ? globally changed v cc(i/o) to the same value as v cc . ? table 2 pin description : updated pin description for eot, dack, diow and dior; also removed table note 3. ? section 8.14.1 power-sharing mode : added remark. ? section 9.5.4 scratch register (address: 78h) : updated the bus reset value. 02 20040629 - preliminary data (9397 750 12979) 01 20040223 - preliminary data (9397 750 11496)
9397 750 13699 philips semiconductors ISP1582 hi-speed usb peripheral controller ? koninklijke philips electronics n.v. 2004. all rights reserved. preliminary data rev. 03 25 august 2004 65 of 66 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 19. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 21. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 22. trademarks acpi is an open industry speci?cation for pc power management, co-developed by intel corp., microsoft corp. and toshiba onnow is a trademark of microsoft corp. softconnect is a trademark of koninklijke philips electronics n.v. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 25 august 2004 document order number: 9397 750 13699 contents philips semiconductors ISP1582 hi-speed usb peripheral controller 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . 10 8.1 dma interface, dma handler and dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.2 hi-speed usb transceiver . . . . . . . . . . . . . . . 11 8.3 mmu and integrated ram . . . . . . . . . . . . . . . 11 8.4 microcontroller interface and microcontroller handler . . . . . . . . . . . . . . . . . 11 8.5 otg srp module . . . . . . . . . . . . . . . . . . . . . . 11 8.6 philips high-speed transceiver . . . . . . . . . . . . 11 8.6.1 philips parallel interface engine (pie) . . . . . . 11 8.6.2 peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 11 8.6.3 hs detection . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.7 philips serial interface engine (sie). . . . . . . . 12 8.8 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.9 system controller . . . . . . . . . . . . . . . . . . . . . . 12 8.10 output pins status. . . . . . . . . . . . . . . . . . . . . . 12 8.11 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.11.1 interrupt output pin . . . . . . . . . . . . . . . . . . . . . 13 8.11.2 interrupt control . . . . . . . . . . . . . . . . . . . . . . . 15 8.12 v bus sensing . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.13 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16 8.14 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.14.1 power-sharing mode. . . . . . . . . . . . . . . . . . . . 18 8.14.2 self-powered mode. . . . . . . . . . . . . . . . . . . . . 20 8.14.3 bus-powered mode. . . . . . . . . . . . . . . . . . . . . 21 9 register description . . . . . . . . . . . . . . . . . . . . 23 9.1 register access . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 initialization registers . . . . . . . . . . . . . . . . . . . 24 9.2.1 address register (address: 00h) . . . . . . . . . . . 24 9.2.2 mode register (address: 0ch) . . . . . . . . . . . . . 25 9.2.3 interrupt con?guration register (address: 10h) 27 9.2.4 otg register (address: 12h) . . . . . . . . . . . . . . 28 9.2.5 interrupt enable register (address: 14h) . . . . . 30 9.3 data ?ow registers . . . . . . . . . . . . . . . . . . . . . 31 9.3.1 endpoint index register (address: 2ch) . . . . . 31 9.3.2 control function register (address: 28h) . . . . 33 9.3.3 data port register (address: 20h) . . . . . . . . . . 33 9.3.4 buffer length register (address: 1ch) . . . . . . 34 9.3.5 buffer status register (address: 1eh) . . . . . . . 35 9.3.6 endpoint maxpacketsize register (address: 04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.7 endpoint type register (address: 08h) . . . . . . 37 9.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.1 dma command register (address: 30h) . . . . 39 9.4.2 dma transfer counter register (address: 34h) 40 9.4.3 dma con?guration register (address: 38h) . . 41 9.4.4 dma hardware register (address: 3ch) . . . . . 42 9.4.5 dma interrupt reason register (address: 50h) 43 9.4.6 dma interrupt enable register (address: 54h) 45 9.4.7 dma endpoint register (address: 58h). . . . . . 45 9.4.8 dma burst counter register (address: 64h). . 46 9.5 general registers . . . . . . . . . . . . . . . . . . . . . . 46 9.5.1 interrupt register (address: 18h). . . . . . . . . . . 46 9.5.2 chip id register (address: 70h) . . . . . . . . . . . 48 9.5.3 frame number register (address: 74h) . . . . . 49 9.5.4 scratch register (address: 78h) . . . . . . . . . . . 49 9.5.5 unlock device register (address: 7ch). . . . . . 50 9.5.6 test mode register (address: 84h) . . . . . . . . . 51 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 52 11 recommended operating conditions . . . . . . 52 12 static characteristics . . . . . . . . . . . . . . . . . . . 53 13 dynamic characteristics . . . . . . . . . . . . . . . . . 54 13.1 register access timing . . . . . . . . . . . . . . . . . . 57 13.2 dma timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14 application information . . . . . . . . . . . . . . . . . 60 15 test information. . . . . . . . . . . . . . . . . . . . . . . . 60 16 package outline . . . . . . . . . . . . . . . . . . . . . . . . 61 17 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 62 17.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 62 17.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 63 17.5 package related soldering information . . . . . . 63 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 64 19 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 65 20 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 21 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 22 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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